1. Field of the Invention
The present invention relates to an on-die termination impedance calibration device, and more particularly to an on-die termination impedance calibration device which is insensitive to the process environment, voltage environment and temperature environment, and can perform the calibration according to its own path and its own schedule.
2. Description of the Prior Art
In general, when a pulse or a signal (hereinafter, referred to as “signal”) is transferred from a bus line to another bus line, a portion of the transferred signal is reflected if impedances of the bus lines are not matched to each other. An on-die termination (hereinafter, referred to as “ODT”) technique is used to reduce such reflection of the signal.
A semiconductor device such as a memory device transmits/receives data and the like to/from an exterior system. When an impedance of a bus line connected between a semiconductor device and an exterior system is not matched with an impedance of a signal line in the semiconductor device which is directly connected to the bus line, transmitted data are reflected.
Recently, high-speed semiconductor devices have generally employed an impedance matching device for preventing the above-mentioned data reflection. Herein, such an impedance matching device is called an ‘ODT device’.
An ODT device is typically installed on a line connected with an input/output pad of a semiconductor device and includes resistance elements. The resistance elements are connected between the line and a terminal at which a predetermined power is supplied, and typically include MOS transistors. The MOS transistor has a channel resistance characteristic of being selectively turned on/off, thereby acting as a resistance element.
FIG. 1 is a block diagram illustrating a conventional ODT impedance calibration device. The conventional ODT impedance calibration device includes an oscillator 110, a maximum counter trigger signal generator 120, an M-bit counter 11, and a pulse generator 130 for a global area, and includes an oscillator 140, a pulse generator 150, a maximum counter trigger signal generator 160, an N-bit counter 12, an ODT impedance calibration unit 170 for a local area.
An internal calibration enable signal ‘int_calen’ is a signal applied from the interior of the semiconductor device in order to perform an ODT impedance calibration mode.
An external calibration enable signal ‘ext_calen’ is applied from an exterior during a normal operation of the semiconductor device. That is, such an external calibration enable signal ‘ext_calen’ is applied to perform an ODT impedance calibration corresponding to property change of the semiconductor device, which is caused by variations of a process environment, a voltage environment, a temperature environment, etc., during a normal operation of the semiconductor device.
The oscillator 110 receives a high-level internal calibration enable signal ‘int_calen’ and outputs an oscillation signal. ‘osc_clk’. The M-bit counter 11 counts the number of pulses of the oscillation signal ‘osc_clk’.
The maximum counter trigger signal generator 120 outputs an output signal ‘int_discal’ under the control of the M-bit counter 11, and changes the output signal ‘int_discal’ from a low level into high level when the M-bit counter 11 counts the Mth pulse of the oscillation signal ‘osc_clk’.
The pulse generator 130 receives the external calibration enable signal ‘ext_calen’ and outputs a pulse signal ‘G_calp’ in synchronization with a rising edge of the oscillation signal ‘osc_clk’.
The oscillator 140 receives the pulse signal ‘G_calp’ output from the pulse generator 130 which is located in the global area, and controls the operation of the pulse generator 150 which is located in the local area. As shown FIG. 4, the pulse generator 150 outputs a pulse signal ‘L_calp’ in synchronization with a rising edge of the pulse signal ‘G_calp’, with a plurality of pulses following the pulse signal ‘L_calp’.
The N-bit counter 12 counts the number of pulses of the pulse generator 150. The maximum counter trigger signal generator 160 is controlled by the N-bit counter 12. When the Nth pulse of the pulse signal ‘L_calp’ is generated, the maximum counter trigger signal generator 160 disables the operation of the pulse generator 150.
The ODT impedance calibration unit 170 receives the pulse signal ‘L_calp’ of the pulse generator 150, and generates and outputs a plurality of control signals ‘code<0:n−1>’.
Accordingly, the ODT impedance is calibrated according to enable states of the control signals ‘code<0:n−1>’.
To be specific, the ODT impedance is calibrated by an ODT block 220. As shown in FIG. 3, the ODT block includes resistors, which have different values (i.e., AΩ, BΩ, CΩ and DΩ) from each other and are connected in parallel with each other, and switching elements. The switching elements are constructed with PMOS transistors which determine the selection of the resistors according to the control signals ‘code<0:n−1>’.
Meanwhile, as shown in FIG. 2, the ODT impedance calibration unit 170 includes a comparator 210, the ODT block 220 and an N-bit counter 230.
The operations of the comparator 210 and the N-bit counter 230 are controlled according to the pulse signal ‘L_calp’ of he pulse generator 150.
The comparator 210 compares a reference voltage ‘Vref’ and the voltage of a line ‘ZQ_in’.
The N-bit counter 230 receives an output signal ‘Com_out’ of the comparator 210 and outputs a control signal ‘code<0:n−1>’ for controlling the ODT block 220.
The ODT block 220 controls the turn-on/off of the PMOS transistors according to the control signal ‘code<0:n−1>’, thereby calibrating the impedance of the line ‘ZQ_in’. A resistance RQ connected to the line ‘ZQ_in’ is included in the ODT impedance.
FIG. 4 is a timing chart for explaining the operation of the conventional ODT impedance calibration device.
In general, in order for a semiconductor device to normally operate, it is necessary to perform an ODT impedance calibration process. The ODT impedance calibration process is employed to establish an optimum ODT impedance value of an internal line of the semiconductor device which receives an exterior signal. It is necessary to optimize the ODT impedance in order to prevent distortion of an input signal and interference between signals.
At the initial state, an ODT impedance calibration operation in the semiconductor device is performed by an internal calibration enable signal ‘int_calen’.
It is necessary to recalibrate the ODT impedance in order to reflect temperature change, voltage change, etc. while the semiconductor device is normally being performed. In this case, the semiconductor device receives an external calibration enable signal ‘ext_calen’ and recalibrates the ODT impedance. However, since the external calibration enable signal ‘ext_calen’ has a predetermined minimum period of time, there is a limitation in the number of times by which the ODT impedance can be recalibrated.
Also, when the operation properties of the oscillator 110 and the oscillator 140, pulse signal ‘L_calp’ and pulse signal ‘G_calp’ may be overlapped with each other as indicated by mark ‘a’ in FIG. 4.
Also, when temperature, voltage and the like of the semiconductor device rapidly change during a normal operation, a problem described below is caused.
That is, as indicated by mark ‘b’ in FIG. 4, since the generation period of the external calibration enable signal ‘ext_calen’ during a normal operation has been decided, the number of pulses of signal ‘L_calp’ is limited even when temperature, voltage and the like rapidly change, so that it is difficult to optimize an ODT impedance.